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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF324C
SST32HF324C32Mb Flash + 4Mb SRAM (x16) MCP ComboMemories
Preliminary Specifications
FEATURES:
* ComboMemory organized as: - 2M x16 Flash + 256K x16 SRAM * Single 2.7-3.3V Read and Write Operations * Concurrent Operation - Read from or Write to SRAM while Erase/Program Flash * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 15 mA (typical) for Flash or SRAM Read - Standby Current: 12 A (typical) * Flexible Erase Capability - Uniform 2 KWord sectors - Uniform 32 KWord size blocks * Erase-Suspend/Erase-Resume Capabilities * Security-ID Feature - User: 128 bits * Fast Read Access Times: - Flash: 70 ns - SRAM: 70 ns * Latched Address and Data for Flash * Flash Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) - Word-Program Time: 7 s (typical) * Flash Automatic Erase and Program Timing - Internal VPP Generation * Flash End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Package Available - 48-ball LBGA (10mm x 12mm x 1.4mm) * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF324C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST's proprietary, high-performance SuperFlash technology. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 sec. To protect against inadvertent flash write, the SST32HF324C devices contain on-chip hardware and software data protection schemes. The SST32HF324C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF324C devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.
(c)2005 Silicon Storage Technology, Inc. S71267-02-000 9/05 1
The SST32HF324C provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST32HF324C devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF324C devices significantly improve performance and reliability while lowering power consumption when compared with multiple chip solutions. The SST32HF324C inherently use less energy during Erase and Program operations than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since, for any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
Flash Word-Program Operation
The flash memory bank of the SST32HF324C devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 10 s. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored.
Device Operation
The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high.
Concurrent Read/Write Operation
The SST32HF324C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. See Figure 22 for a flowchart. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE
Flash Program/Erase Program/Erase SRAM Read Write
Flash Sector-/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF324C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines AMS-A11 are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines AMS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.
The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.
Flash Read Operation
The Read operation of the SST32HF324C devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 5 for further details.
(c)2005 Silicon Storage Technology, Inc.
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Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Erase-Suspend/-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence.
Write Operation Status Detection
The SST32HF324C provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Flash Chip-Erase Operation
The SST32HF324C provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 5 for the command sequence, Figure 9 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Flash Data# Polling (DQ7)
When the SST32HF324C flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 19 for a flowchart.
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Preliminary Specifications
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 19 for a flowchart. TABLE 1: WRITE OPERATION STATUS
Status
Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- Erase-Suspended Sector/Block Program
Flash Software Data Protection (SDP)
The SST32HF324C provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF324C devices are shipped with the software data protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence.
SRAM Read
The SRAM Read operation of the SST32HF324C is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 2, for further details.
DQ7
DQ7# 0 1
DQ6
Toggle Toggle 1
DQ2
No Toggle Toggle Toggle
SRAM Write
Data Data Data
DQ7#
Toggle
N/A
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Note: DQ7 and DQ2 require a valid address when reading status information.
Flash Memory Data Protection
The SST32HF324C flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes.
The SRAM Write operation of the SST32HF324C is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 3 and 4, for further details.
Product Identification
The Product Identification mode identifies the devices as the SST32HF324C and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the flash Write operation. This prevents inadvertent writes during power-up or power-down.
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Preliminary Specifications Tables 4 and 5 for software operation, Figure 13 for the software ID entry and read timing diagram and Figure 20 for the ID entry command sequence flowchart. TABLE 2: PRODUCT IDENTIFICATION
Address Manufacturer's ID Device ID SST32HF324C 0001H 235BH
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Security ID
The SST32HF324C device offers one 128-bit Security ID space. This space is left un-programmed for the customer to program as desired. To program the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, the Sec ID segment cannot be erased. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 5 for more details.
Data BFH
0000H
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 5 for software command codes, Figure 14 for timing waveform and Figure 20 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
AMS(1)-A0
UBS# LBS# BES# BEF# OE# WE#
Control Logic
I/O Buffers
DQ15 - DQ8 DQ7 - DQ0
Address Buffers & Latches
SuperFlash Memory
1267 B1.0
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Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
TOP VIEW (balls facing down)
SST32HF324C
6 5 4 3 2 1
BES# VSS DQ1 A10 DQ5 DQ2 OE# DQ7 DQ4 A11 A13 A8 A5
A1 A0 DQ0 DQ8
A2 A3 A6
A4 A7 A18
A19 A20 NC
A9 A14 A15
DQ3 DQ12
A12 LBS# DQ6 DQ15
WE# VDDS A16
VSS
DQ9 DQ11 DQ13 DQ14
ABCDEFGH
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION
Symbol AMS1-A0 DQ15-DQ0 Pin Name Address Inputs Data Input/output Functions To provide flash addresses: A20-A0 SRAM addresses: A17-A0
To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. To activate the SRAM memory bank when BES# is low. To activate the flash memory bank when BEF# is low. To gate the data output buffers. To control the Write operations. 2.7-3.3V Power Supply to flash only. 2.7-3.3V Power Supply to SRAM only To enable DQ15-DQ8 To enable DQ7-DQ0 Unconnected Pins
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BES# BEF# OE# WE# VDDF VDDS VSS UBS# LBS# NC
SRAM Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply (Flash) Power Supply (SRAM) Ground Upper Byte Control (SRAM) Lower Byte Control (SRAM) No Connection
1. AMS=Most significant address
(c)2005 Silicon Storage Technology, Inc.
1267 48-lbga P2.1
A17 UBS# BEF# DQ10 VDDF
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Preliminary Specifications TABLE 4: OPERATION MODES SELECTION
Mode Not Allowed Flash Read Program Erase SRAM Read VIL VIL VIL Write VIL VIL VIL Standby Flash Write Inhibit VIHC X X X Output Disable VIH VIL VIL Product Identification Software Mode VIH VIL VIL VIH X X Manufacturer's ID (00BFH) Device ID3 A19-A1=VIL, A0=VIH (See Table 4)
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BES#1 BEF#1 OE# WE# UBS# LBS# VIL VIH VIH X VIL VIL VIL VIL X2 VIL VIH VIH X VIH VIL VIL X X X X X X X X
DQ15 to DQ8 X DOUT DIN X
DQ7 to DQ0 X DOUT DIN X
Address X AIN AIN Sector or Block address, XXH for Chip-Erase AIN AIN AIN AIN AIN AIN X X X X X X X
VIH VIH VIH VIH VIH VIH VIHC X X VIH VIL VIH VIH
VIL VIL VIL X X X X VIL X X VIH X VIH
VIH VIH VIH VIL VIL VIL X X VIH X VIH X VIH
VIL VIL VIH VIL VIL VIH X X X X X VIH X
VIL VIH VIL VIL VIH VIL X X X X X VIH X
DOUT DOUT High Z DIN DIN High Z High Z
DOUT High Z DOUT DIN High Z DIN High Z
High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z / DOUT High Z High Z High Z High Z High Z High Z
1. Do not apply BES#=VIL and BEF#=VIL at the same time 2. X can be VIL or VIH, but no other value. SST Manufacturer's ID = 00BFH, is read with A0=0, 3. With AMS-A1 = 0; SST32HF324C Device ID = 235BH, is read with A0=1
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Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications TABLE 5: SOFTWARE COMMAND SEQUENCE
Command Sequence
Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5
1st Bus Write Cycle Addr1 5555H 5555H 5555H 5555H XXXXH XXXXH 5555H 5555H 5555H 5555H 5555H XXH Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH F0H
2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H
3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 80H
4th Bus Write Cycle Addr1 WA3 5555H 5555H 5555H Data2 Data AAH AAH AAH
5th Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H
6th Bus Write Cycle Addr1 SAX4 BAX
4
Data2 30H 50H 10H
5555H
2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
55H 55H 55H 55H 55H
5555H 5555H 5555H 5555H 5555H
88H A5H 85H 90H F0H WA6 XXH6 Data 0000H
User Security ID Word-Program User Security ID Program Lock-Out Software ID Entry7,8 Software ID /Sec ID Exit Exit9
Software ID Exit9 /Sec ID Exit
T5.1 1267
1. Address format A14-A0 (Hex). Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF324C. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A20 for SST32HF324C. 5. With A20-A5 = 0; Sec ID is read with A4-A0, User ID is read with A4 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST32HF324C Device ID = 235BH, is read with A0 = 1, AMS = Most significant address AMS = A20 for SST32HF324C. 9. Both Software ID Exit operations are equivalent
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Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS 2. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Commercial Extended Ambient Temp 0C to +70C -20C to +85C VDD 2.7-3.3V 2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 16 and 17
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Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits Symbol IDD Parameter Active VDD Current Read Flash SRAM Concurrent Operation Write1 Flash SRAM ISB ILI ILO VIL VILC VIH VIHC VOLF VOHF VOLS VOHS Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Low Voltage Flash Output High Voltage SRAM Output Low Voltage SRAM Output High Voltage 2.2 0.7 VDD 35 30 30 1 10 0.8 0.3 mA mA A A A V V V V 0.2 V V 0.4 V V 18 30 40 mA mA mA Min Max Units Test Conditions Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH BEF#=VIH, BES#=VIL VDD = VDD Max, BEF#=BES#=VIHC VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min IOL =1 mA, VDD=VDD Min IOH =-500 A, VDD=VDD Min
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VDD-0.3 VDD-0.2
1. IDD active while Erase or Program is in progress.
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Program/Erase Operation
Minimum 100 100
Units s s
T7.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (TA = 25C, f=1 Mhz, other pins open)
Parameter CI/O1 CIN
1
Description I/O Pin Capacitance Input Capacitance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 12 pF
T8.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: FLASH RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T9.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
10
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
AC CHARACTERISTICS
TABLE 10: SRAM READ CYCLE TIMING PARAMETERS
Symbol TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
1
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# to Active Output Output Enable to Active Output UBS#, LBS# to Active Output BES# to High-Z Output Output Disable to High-Z Output
Min 70
Max 70 70 35 70
Units ns ns ns ns ns ns ns ns
0 0 0 25 0 10 25 35
ns ns ns ns
T10.0 1267
TOHZS1 TBYHZS TOHS
1
UBS#, LBS# to High-Z Output Output Hold from Address Change
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# to End-of-Write Output Disable from WE# Low Output Enable from WE# High Data Set-up Time Data Hold from Write Time 0 30 0 Min 70 60 60 0 60 0 60 30 Max Units ns ns ns ns ns ns ns ns ns ns ns
T11.0 1267
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
11
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Low to Active Output OE# Low to Active Output BEF# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 0 0 0 20 20 Min 70 70 70 35 Max Units ns ns ns ns ns ns ns ns ns
T12.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH TSE TBE TSCE
1
Parameter Word-Program Time Address Setup Time Address Hold Time WE# and BEF# Setup Time WE# and BEF# Hold Time OE# High Setup Time OE# High Hold Time BEF# Pulse Width WE# Pulse Width WE# Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase
Min 0 30 0 0 0 10 40 40 30 30 30 0
Max 10
Units s ns ns ns ns ns ns ns ns ns ns ns ns
TIDA1
150 25 25 50
ns ms ms ms
T13.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
12
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
TRCS ADDRESSES AMSS-0 TAAS BES# TBES TBLZS OE# TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID
1267 F02.0
TOHS
TBHZS TOES TOHZS TBYES TBYHZS
Note: AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESSES AMSS3-0 TASTS WE# TAWS TBWS BES# TBYWS UBS#, LBS# TODWS TDSS DQ15-8, DQ7-0 NOTE 2 TOEWS TDHS NOTE 2
1267 F03.0
TWPS
TWRS
VALID DATA IN
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance. If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
13
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
TWCS ADDRESSES AMSS3-0 TWPS WE# TBWS BES# TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TDHS NOTE 2
1267 F04.0
TWRS
TBYWS
VALID DATA IN
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
TRC ADDRESS AMS-0
TAA
BEF#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
1267 F05.0
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C
FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
14
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TWP WE# TAS OE# TCH BEF# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
1267 F06.0
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value
FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 5555 TAH TCP BEF# TAS OE# TCH WE# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA)
1267 F07.0
2AAA
5555
ADDR TDH
TCPH
TDS
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value
FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
15
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
ADDRESSES AMSF-0 TCE BEF# TOEH OE# TOE WE# TOES
DQ7
Data
Data#
Data#
Data
1267 F08.0
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C
FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES AMSF-0 TCE BEF# TOEH OE# TOE TOES
WE#
DQ6 and DQ2
TWO READ CYCLES WITH SAME OUTPUTS
1267 F09.0
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
16
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
BEF#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX10 SW5
1267 F10.0
Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13) AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX
TBE
BEF#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX50 SW5
1267 F11.0
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) BAX = Block Address X can be VIL or VIH, but no other value.
FIGURE 11: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
17
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX
TSE
BEF#
OE# TWP WE#
DQ15-0
XXAA SW0
XX55 SW1
XX80 SW2
XXAA SW3
XX55 SW4
XX30 SW5
1267 F12.0
Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) SAX = Sector Address X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
18
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
THREE-WORD SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2 TAA 00BF MFG ID DEVICE ID
1267 F13.0
TIDA
Note: X can be VIL or VIH, but no other value. Device ID - See Table 2 on page 5
FIGURE 13: SOFTWARE ID ENTRY AND READ
THREE-WORD SEQUENCE FOR SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
OE# TWP WE# TWHP
1267 F14.0
SW0
SW1
SW2
Note: X can be VIL or VIH, but no other value.
FIGURE 14: SOFTWARE ID EXIT AND RESET
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
19
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A20-0 5555 2AAA 5555
BEF#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX88 SW2
1267 F22.0
TIDA
TAA
Note: X can be VIL or VIH, but no other value.
FIGURE 15: SEC ID ENTRY
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
20
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1267 F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5VDD) and VOT (0.5VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
1267 F16.0
FIGURE 17: A TEST LOAD EXAMPLE
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
21
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Start
Write data: XXAAH Address: 5555H
Write data: XX55H Address: 2AAAH
Write data: XXA0H Address: 5555H
Write Word Address/Word Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1267 F17.0
Note: X can be VIL or VIH, but no other value
FIGURE 18: WORD-PROGRAM ALGORITHM
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
22
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, or TBE
Read word
Read DQ7
Program/Erase Completed
Read same word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
1267 F18.0
FIGURE 19: WAIT OPTIONS
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
23
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Software Product ID Entry Command Sequence
Sec ID Query Entry Command Sequence
Software Product ID/Sec ID Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address: XXH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
Load data: XX90H Address: 5555H
Load data: XX88H Address: 5555H
Load data: XXF0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read Software ID
Read Sec ID
Return to normal operation
1267 F19.1
X can be VIL or VIH, but no other value
FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
24
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
1267 F20.0
Note: X can be VIL or VIH, but no other value.
FIGURE 21: ERASE COMMAND SEQUENCE
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
25
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
Concurrent Operation Load SDP Command Sequence
Flash Program/Erase Initiated
Wait for End of Write Indication
Read or Write SRAM
End Wait
Flash Operation Completed
End Concurrent Operation
1267 F21.0
FIGURE 22: CONCURRENT OPERATION FLOWCHART
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
26
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 XX Suffix2 XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 leads or balls Package Type LB = LBGA (10mm x 12mm x 1.4mm) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Density 324 = 32 Mbit Flash + 4 Mbit SRAM Voltage H = 2.7-3.3V Product Series 32 = MPF + SRAM ComboMemory
SST32HFxxxC - XXX
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
Valid combinations for SST32HF324C SST32HF324C-70-4C-LBK SST32HF324C-70-4C-LBKE SST32HF324C-70-4E-LBK SST32HF324C-70-4E-LBKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2005 Silicon Storage Technology, Inc.
S71267-02-000
9/05
27
Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
12.00 0.20
BOTTOM VIEW
7.0 1.0
6 5 4
10.00 0.20 5.0
6 5 4 3 2 1
1.0 0.50 0.05 (48X) A B C D E F G H 1.4 Max H G F E D C B A A1 CORNER
3 2 1
A1 CORNER
SIDE VIEW
SEATING PLANE 0.40 0.05 Note:
0.12
1mm
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.4 mm ( 0.05 mm)
48-lbga-LBK-10x12-500mic-2
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM SST PACKAGE CODE: LBK TABLE 14: REVISION HISTORY
Number 00 01 Description Date Jul 2004 May 2005
* * * *
Initial Release Removed all 16 Mbit devices and related MPNs Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 27 Added the solder reflow temperature to the "Absolute Maximum Stress Ratings" on page 9. Added User Security ID feature
02
*
Sep 2005
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2005 Silicon Storage Technology, Inc. S71267-02-000 9/05
28

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